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general description the max5048a/max5048b are high-speed mosfet drivers capable of sinking/sourcing 7.6a/1.3a peak cur- rents. these devices take logic input signals and drive a large external mosfet. the max5048a/max5048b have inverting and noninverting inputs that give the user greater flexibility in controlling the mosfet. they feature two separate outputs working in complementary mode, offering flexibility in controlling both turn-on and turn-off switching speeds. the max5048a/max5048b have internal logic circuitry, which prevents shoot-through during output state changes. the logic inputs are protected against volt- age spikes up to +14v, regardless of v+ voltage. propagation delay time is minimized and matched between the inverting and noninverting inputs. the max5048a/max5048b have very fast switching times combined with very short propagation delays (12ns typ), making them ideal for high-frequency circuits. the max5048a/max5048b operate from a +4v to +12.6v single power supply and typically consume 0.95ma of supply current. the max5048a has cmos input logic levels, while the max5048b has standard ttl input logic levels. these devices are available in space-saving 6-pin sot23 and tdfn packages. applications power mosfet switching switch-mode power supplies dc-dc converters motor control power-supply modules features ? independent source-and-sink outputs for controllable rise and fall times ? +4v to +12.6v single power supply ? 7.6a/1.3a peak sink/source drive current ? 0.23 ? open-drain n-channel sink output ? 2 ? open-drain p-channel source output ? 12ns (typ) propagation delay ? matching delay time between inverting and noninverting inputs ? v cc /2 cmos (max5048a)/ttl (max5048b) logic inputs ? 1.6v input hysteresis ? up to +14v logic inputs (regardless of v+ voltage) ? low input capacitance: 2.5pf (typ) ? -40? to +125? operating temperature range ? 6-pin sot23 and tdfn packages max5048 7.6a, 12ns, sot23/tdfn, mosfet driver ________________________________________________________________ maxim integrated products 1 p_out gnd n_out 16 in+ 5 in- v+ max5048a max5048b sot23 top view 2 34 pin configurations ordering information max5048a max5048b p_out n_out in- gnd in+ v+ v+ n t ypical operating circuit 19-2419; rev 4; 7/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package logic input top mark max5048aaut-t -40? to +125? 6 sot23-6 v cc /2 cmos abec max5048baut-t -40? to +125? 6 sot23-6 ttl abed MAX5048AATT-t -40? to +125? 6 tdfn-6 v cc /2 cmos akv max5048batt-t -40? to +125? 6 tdfn-6 ttl akw pin configurations continued at end of data sheet.
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = +12v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltages referenced to gnd v+ ...........................................................................-0.3v to +13v in+, in-...................................................................-0.3v to +14v n_out, p_out ............................................-0.3v to (v+ + 0.3v) n_out continuous output current (note 1) ....................390ma p_out continuous output current (note 1).....................100ma continuous power dissipation* (t a = +70?) 6-pin sot23 (derate 9.1mw/? above +70?)............727mw junction to case thermal resistance, jc (sot23)....75?/w 6-pin tdfn (derate 18.2mw/? above +70?) .........1454mw junction to case thermal resistance, jc (tdfn) ....8.5?/w operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? note 1: continuous output current is limited by the power dissipation of the package. *as per jedec51 standard. parameter symbol conditions min typ max units power supply v+ operating range v+ 4.0 12.6 v v+ undervoltage lockout uvlo v+ rising 3.25 3.6 4.00 v v+ undervoltage lockout hysteresis 400 mv v+ undervoltage lockout to output delay time v+ rising 300 ns v+ supply current i+ in+ = in- = v+ 0.95 1.5 ma n-channel output t a = +25? 0.23 0.26 v+ = +10v, i n-out = -100ma t a = +125? 0.38 0.43 t a = +25? 0.24 0.28 driver output resistance pulling down (max5048aaut/ max5048baut) r on-n v+ = +4.5v, i n-out = -100ma t a = +125? 0.40 0.47 ? ? ? p-channel output t a = +25? 2.00 3.00 v+ = +10v, i p-out = 50ma t a = +125? 2.85 4.30 t a = +25? 2.20 3.30 driver output resistance pulling up (max5048aaut/ max5048baut) r on-p v+ = +4.5v, i p-out = 50ma t a = +125? 3.10 4.70 ?
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = +12v, t a = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units t a = +25? 2.08 3.08 v+ = +10v, i p-out = 50ma t a = +125? 2.93 4.38 t a = +25? 2.28 3.38 driver output resistance pulling up (MAX5048AATT/ max5048batt) r on-p v+ = +4.5v, i p-out = 50ma t a = +125? 3.18 4.78 ? logic input max5048a 0.67 x v+ logic 1 input voltage v ih max5048b 2.4 v max5048a 0.33 x v+ logic 0 input voltage v il max5048b 0.8 v max5048a 1.6 logic-input hysteresis v hys max5048b 0.68 v logic-input current v in_ = v+ or 0 0.001 10 ? input capacitance c in 2.5 pf switching characteristics for v+ = +10v c l = 1000pf 8 c l = 5000pf 45 rise time t r c l = 10,000pf 82 ns c l = 1000pf 3.2 c l = 5000pf 7.5 fall time t f c l = 10,000pf 12.5 ns turn-on propagation delay time t d-on figure 1, c l = 1000pf (note 3) 7 12 25 ns turn-off propagation delay time t d-off figure 1, c l = 1000pf (note 3) 7 12 25 ns break-before-make time 2.5 ns switching characteristics for v+ = +4.5v c l = 1000pf 12 c l = 5000pf 41 rise time t r c l = 10,000pf 74 ns c l = 1000pf 3.0 c l = 5000pf 7.0 fall time t f c l = 10,000pf 11.3 ns turn-on propagation delay time t d-on figure 1, c l = 1000pf (note 3) 8 14 27 ns turn-off propagation delay time t d-off figure 1, c l = 1000pf (note 3) 8 14 27 ns break-before-make time 4.2 ns note 2: all dc specifications are 100% tested at t a = +25?. specifications over -40? to +125? are guaranteed by design. note 3: guaranteed by design, not production tested.
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 4 _______________________________________________________________________________________ t ypical operating characteristics (c l = 1000pf, t a = +25?, unless otherwise noted.) rise time vs. supply voltage max5048 toc01 supply voltage (v) rise time (ns) 10 8 6 8 11 14 17 20 5 412 t a = +125 c t a = 0 c t a = +85 c t a = +25 c t a = -40 c fall time vs. supply voltage max5048 toc02 supply voltage (v) fall time (ns) 10 8 6 2.5 3.5 4.5 5.0 6.0 2.0 412 t a = +125 c t a = -40 c t a = 0 c t a = +85 c t a = +25 c 3.0 5.5 4.0 max5048 toc03 supply voltage (v) propagation delay (ns) 10 8 6 12 14 16 18 20 10 412 t a = +125 c t a = -40 c t a = 0 c t a = +85 c t a = +25 c propagation delay time, low-to-high vs. supply voltage max5048 toc04 supply voltage (v) propagation delay (ns) 10 8 6 12 14 16 18 20 10 412 t a = +125 c t a = -40 c t a = 0 c t a = +85 c t a = +25 c propagation delay time, high-to-low vs. supply voltage supply current vs. supply voltage max5048 toc05 supply voltage (v) supply current (ma) 10 8 6 2 4 6 8 10 12 0 412 duty cycle = 50% v+ = +10v, c l = 0 1mhz 500khz 40khz 75khz 100khz supply current vs. load capacitance max5048 toc06 load capacitance (pf) supply current (ma) 1600 1200 400 800 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 02 000 v+ = +10v f = 100khz duty cycle = 50% supply current vs. temperature max5048 toc07 temperature ( c) supply current (ma) 100 75 50 25 0 -25 1.3 1.4 1.5 1.6 1.7 1.8 1.2 -50 125 v+ = +10v f = 100khz, c l = 0 duty cycle = 50% max5048a input threshold voltage vs. supply voltage max5048 toc08 supply voltage (v) input threshold voltage (v) 10 8 6 1 2 3 4 5 6 7 8 0 412 rising falling max5048a supply current vs. input voltage max5048 toc09 input voltage (v) supply current (ma) 10 8 6 4 2 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0.8 012 input high-to-low input low-to-high
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver _______________________________________________________________________________________ 5 input voltage vs. output voltage (v+ = +4v, c l = 5000pf) max5048 toc10 in+ 2v/div output 2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 10,000pf) max5048 toc11 in+ 2v/div output 2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 5000pf) max5048 toc12 in+ 2v/div output 2v/div 20ns/div input voltage vs. output voltage (v+ = +4v, c l = 10,000pf) max5048 toc13 in+ 2v/div output 2v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 5000pf) max5048 toc14 in+ 5v/div output 5v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 10,000pf) max5048 toc15 in+ 5v/div output 5v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 5000pf) max5048 toc16 in+ 5v/div output 5v/div 20ns/div input voltage vs. output voltage (v+ = +12v, c l = 10,000pf) max5048 toc17 in+ 5v/div output 5v/div 20ns/div t ypical operating characteristics (continued) (c l = 1000pf, t a = +25?, unless otherwise noted.)
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 6 _______________________________________________________________________________________ detailed description logic inputs the max5048a/max5048bs?logic inputs are protected against voltage spikes up to +14v, regardless of the v+ voltage. the low 2.5pf input capacitance of the inputs reduces loading and increases switching speed. these devices have two inputs that give the user greater flexi- bility in controlling the mosfet. table 1 shows all pos- sible input combinations. the difference between the max5048a and the max5048b is the input threshold voltage. the max5048a has v cc /2 cmos logic-level thresholds, while the max5048b has ttl logic-level thresholds (see the electrical characteristics ). for v+ above 5.5v, v ih (typ) = 0.5x(v+) + 0.8v and v il (typ) = 0.5x(v+) - 0.8v. as v+ is reduced from 5.5v to 4v, v ih and v il gradually approach v ih (typ) = 0.5x(v+) + 0.65v and v il (typ) = 0.5x(v+) - 0.65v. connect in+ to v+ or in- to gnd when not used. alternatively, the unused input can be used as an on/off pin (see table 1). undervoltage lockout (uvlo) when v+ is below the uvlo threshold, the n-channel is on and the p-channel is off, independent of the state of the inputs. the uvlo is typically 3.6v with 400mv typical hysteresis to avoid chattering. driver outputs the max5048a/max5048b provide two separate out- puts. one is an open-drain p-channel, the other an open-drain n-channel. they have distinct current sourc- ing/sinking capabilities to independently control the rise and fall times of the mosfet gate. add a resistor in series with p_out/n_out to slow the corresponding rise/fall time of the mosfet gate. applications information supply bypassing, device grounding, and placement ample supply bypassing and device grounding are extremely important because when large external capacitive loads are driven, the peak current at the v+ pin can approach 1.3a, while at the gnd pin the peak current can approach 7.6a. v cc drops and ground shifts are forms of negative feedback for inverters and, if excessive, can cause multiple switching when the in- input is used and the input slew rate is low. the device driving the input should be referenced to the max5048a/max5048b gnd pin especially when the in- input is used. ground shifts due to insufficient device grounding may disturb other circuits sharing the same ac ground return path. any series inductance in the v+, p_out, n_out and/or gnd paths can cause oscilla- tions due to the very high di/dt that results when the max5048a/max5048b are switched with any capacitive load. a 0.1? or larger value ceramic capacitor is rec- ommended bypassing v+ to gnd and placed as close to the pins as possible. when driving very large loads (e.g., 10nf) at minimum rise time, 10? or more of paral- lel storage capacitance is recommended. a ground plane is highly recommended to minimize ground return resistance and series inductance. care should be taken to place the max5048a/max5048b as close as possi- ble to the external mosfet being driven to further mini- mize board inductance and ac path resistance. power dissipation power dissipation of the max5048a/max5048b con- sists of three components, caused by the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). the sum of these components must be kept below the maximum power-dissipation limit. pin description pin name function 1v+ power supply. bypass to gnd with a 0.1? ceramic capacitor. 2 p_out p-channel open-drain output. sources current for mosfet turn-on. 3 n_out n-channel open-drain output. sinks current for mosfet turn-off. 4 gnd ground 5 in- inverting logic input terminal. connect to gnd when not used. 6 in+ noninverting logic input terminal. connect to v+ when not used. ?p exposed paddle. connect to gnd. solder ep to the gnd plane for improved thermal performance. in+ in- p-channel n-channel ll off on lh off on hl on off hh off on table 1. truth table l = logic low h = logic high
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver _______________________________________________________________________________________ 7 the quiescent current is 0.95ma typical. the current required to charge and discharge the internal nodes is frequency dependent (see the typical operating characteristics ). the max5048a/max5048b power dis- sipation when driving a ground referenced resistive load is: p = d x r on(max) x i load 2 where d is the fraction of the period the max5048a/ max5048bs?output pulls high, r on (max) is the maxi- mum on-resistance of the device with the output high (p-channel), and i load is the output load current of the max5048a/max5048b. for capacitive loads, the power dissipation is: p = c load x (v+) 2 x freq where c load is the capacitive load, v+ is the supply voltage, and freq is the switching frequency. layout information the mosfet drivers max5048a/max5048b source- and-sink large currents to create very fast rise and fall edges at the gate of the switching mosfet. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. the following pc board layout guidelines are recommended when designing with the max5048a/max5048b: place one or more 0.1? decoupling ceramic capaci- tor(s) from v+ to gnd as close to the device as possi- ble. at least one storage capacitor of 10? (min) should be located on the pc board with a low resis- tance path to the v+ pin of the max5048a/max5048b. there are two ac current loops formed between the device and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from n_out of the max5048a/max5048b to the mosfet gate to the mosfet source and to gnd of the max5048a/ max5048b. when the gate of the mosfet is being pulled high, the active current loop is from p_out of the max5048a/max5048b to the mosfet gate to the mosfet source to the gnd terminal of the decoupling capacitor to the v+ terminal of the decoupling capacitor and to the v+ terminal of the max5048a/max5048b. while the charging current loop is important, the discharging current loop is crit- ical. it is important to minimize the physical distance and the impedance in these ac current paths. in+ v il 90% 10% t d?ff p_out and n_out tied together t d?n t f t r in+ in- v+ v+ c l n_out gnd p_out test circuit timing diagram max5048a max5048b input output v ih figure 1. timing diagram and test circuit
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 8 _______________________________________________________________________________________ in a multilayer pc board, the component surface layer surrounding the max5048a/max5048b should consist of a gnd plane containing the discharging and charging current loops. chip information transistor count: 676 process: bicmos break- before- make control p n n_out gnd in- in+ p_out v+ max5048a max5048b figure 2. max5048a/max5048b functional diagram max5048a max5048b p_out n_out in- gnd in+ v+ v s v+ (4v to 12.6v) figure 3. noninverting application max5048a max5048b p_out n_out in- gnd in+ v+ v s v out from pwm controller (boost) v+ (4v to 12.6v) figure 4. boost converter max5048a max5048b p_out n_out in- gnd in+ v+ max5048a/ max5048b p_out n_out in- gnd in+ v+ from pwm controller (buck) v out 4v to 12v p n figure 5. max5048a/max5048b in high-power synchronous buck converter
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver _______________________________________________________________________________________ 9 p_out gnd n_out 16 in+ 5 in- v+ max5048a max5048b tdfn 3mm x 3mm top view 2 3 exposed pad 4 pin configurations (continued) 6lsot.eps package outline, sot 6l body 21-0058 1 1 g package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver 10 ______________________________________________________________________________________ 6, 8, &10l, dfn thin.eps l c l c pin 1 index area d e l e l a e e2 n g 1 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm -drawing not to scale- k e [(n/2)-1] x e ref. pin 1 id 0.35x0.35 detail a b d2 a2 a1 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max5048 7.6a, 12ns, sot23/tdfn, mosfet driver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.300.10 1.500.10 6 t633-1 0.95 bsc mo229 / weea 1.90 ref 0.400.05 1.95 ref 0.300.05 0.65 bsc 2.300.10 8 t833-1 2.00 ref 0.250.05 0.50 bsc 2.300.10 10 t1033-1 2.40 ref 0.200.05 - - - - 0.40 bsc 1.700.10 2.300.10 14 t1433-1 1.500.10 1.500.10 mo229 / weec mo229 / weed-3 0.40 bsc - - - - 0.200.05 2.40 ref t1433-2 14 2.300.10 1.700.10 t633-2 6 1.500.10 2.300.10 0.95 bsc mo229 / weea 0.400.05 1.90 ref t833-2 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref t833-3 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref -drawing not to scale- g 2 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm downbonds allowed no no no no yes no yes no package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > p ower and battery m anagement a utomotive max5048 7.6a, 12ns, sot23/tdfn mosfet driver quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-16 of 16 m ax5048 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5048baut#g16 sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6fh-6 * -40c to +125c rohs/lead-free: rohs qualified materials analysis max5048aaut#g16 sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6fh-6 * -40c to +125c rohs/lead-free: rohs qualified materials analysis max5048aaut#tg16 sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6fh-6 * -40c to +125c rohs/lead-free: rohs qualified materials analysis max5048baut#tg16 sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6fh-6 * -40c to +125c rohs/lead-free: rohs qualified materials analysis max5048baut sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6f-6 * -40c to +125c rohs/lead-free: no materials analysis max5048aaut sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6f-6 * -40c to +125c rohs/lead-free: no materials analysis max5048aaut-t sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6f-6 * -40c to +125c rohs/lead-free: no materials analysis max5048baut-t sot-23;6 pin;9 mm dwg: 21-0058i (pdf) use pkgcode/variation: u6f-6 * -40c to +125c rohs/lead-free: no materials analysis MAX5048AATT+ thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633+2 * -40c to +125c rohs/lead-free: lead free materials analysis max5048batt thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633-2 * -40c to +125c rohs/lead-free: no materials analysis max5048batt+ thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633+2 * -40c to +125c rohs/lead-free: lead free materials analysis MAX5048AATT thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633-2 * -40c to +125c rohs/lead-free: no materials analysis max5048batt+t thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633+2 * -40c to +125c rohs/lead-free: lead free materials analysis
max5048batt-t thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633-2 * -40c to +125c rohs/lead-free: no materials analysis MAX5048AATT-t thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633-2 * -40c to +125c rohs/lead-free: no materials analysis MAX5048AATT+t thin qfn (dual);6 pin;10 mm dwg: 21-0137i (pdf) use pkgcode/variation: t633+2 * -40c to +125c rohs/lead-free: lead free materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits doc ument ref.: 1 9 -2 4 1 9 ; rev 4 ; 2 0 0 5 -0 9 -2 7 t his page las t modified: 2 0 0 7 -0 7 -2 7 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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